Single-board computers (SBCs) do not have a single universal target for “total timing.” The right timing budget depends on the board, the operating system, and the specific workload. In practice, engineers define end-to-end latency targets based on the task, then measure and optimize from input to output. For real-time microcontroller-like tasks, timing can be microseconds; for Linux-based SBCs, end-to-end latency typically ranges from hundreds of microseconds to several milliseconds, with higher budgets for complex I/O or network-heavy applications.
What total timing means on an SBC
In the SBC context, “total timing” usually refers to the full delay from a triggering event to the completion of the required action or observation of the result. It collects every hop in the path: CPU computation, operating system scheduling, device-driver overhead, bus and peripheral delays, storage or network access, and any buffering or queuing in the software stack. Understanding these components helps set a realistic timing budget for a project.
Before diving into the details, it’s useful to identify the main contributors to total timing on your SBC. The following list outlines the core factors that typically shape end-to-end latency.
- CPU processing time for your application code and data handling
- Operating system scheduling and interrupt latency, especially under non-real-time kernels
- Driver and kernel overhead for I/O paths (GPIO, SPI, I2C, UART, USB, PCIe)
- Peripheral device delays (sensors, actuators, DAC/ADC blocks)
- Storage access time (SD card, eMMC, NVMe) and file system overhead
- Network latency for Ethernet/Wi‑Fi and any protocol stack processing
- Thermal throttling and dynamic clock scaling that affect available processing power
- Bus arbitration and chipset-level delays on the SBC’s SoC
Understanding these components helps you set a realistic timing budget and prioritize optimizations. The next sections translate these ideas into practical targets by use case and offer measurement approaches.
Common timing targets by use case
Different applications demand different levels of responsiveness. The following ranges serve as rough guidelines to help you plan projects, test performances, and decide when to adopt real-time approaches or offload time-critical tasks.
- Real-time control and robotics (sensors to actuators): sub-millisecond to a few milliseconds end-to-end latency is ideal; 1 ms is a common practical target, with 100 µs–1 ms achievable on dedicated real-time systems or microcontrollers. On general-purpose Linux SBCs, expect typical end-to-end latency in the 1–10 ms range for well-structured, optimized paths, and higher under heavy load.
- Audio and live media processing: latency budgets often aim for under 10–50 ms to feel responsive in interactive situations, with stricter requirements for professional audio workflows.
- Interactive user interfaces and gaming on networked SBCs: many applications target 20–100 ms total latency for a smooth experience, though some high-performance setups push toward 10–20 ms.
- Data collection, logging, and batch processing (offline workflows): latency tolerance is higher; tens to hundreds of milliseconds or more can be acceptable if real-time interaction is not required.
These figures are indicative. Your project’s constraints—such as required refresh rates, control loop frequency, user expectations, and safety considerations—will drive the final targets. If your use case sits between categories, start with a conservative budget and refine with measurements.
Measuring and improving timing on an SBC
Measuring end-to-end timing requires careful setup and repeatable tests. The steps below outline a pragmatic approach to quantify total timing and identify bottlenecks.
- Define the measurement goal and success criteria: specify the input event, the exact output or observable result, and the acceptable latency range.
- Choose a measurement method: use high-resolution timers (system clock, monotonic clock), hardware timers, and repeatable test benches. For Linux, consider perf, ftrace, and eBPF-based latency probes; for real-time tasks, cyclictest and rt-tests can reveal scheduler latency.
- Instrument the path: log timestamps at key stages (input capture, processing start/end, I/O completion, output generation) to compute end-to-end latency.
- Control the environment: use a stable power supply, minimize background processes, and, if possible, isolate CPUs or use a real-time kernel (PREEMPT_RT) to reduce jitter and preemption variability.
- Analyze results and identify bottlenecks: look for lengthy kernel paths, driver delays, or peripheral bottlenecks, and separate CPU-bound from I/O-bound delays.
- Iterate optimizations: options include real-time kernels, CPU isolation, faster storage, streamlined drivers, dedicated microcontroller offloads, or moving time-critical tasks to an MCU or FPGA co-processor.
After measuring and optimizing, verify with multiple runs under representative workloads, and document the measured latency distribution (minimum, median, 90th/99th percentile, maximum) to understand both typical performance and worst-case behavior.
Practical optimization strategies by task
Real-time control and low-latency I/O
Consider using a real-time capable kernel, CPU isolation for the control thread, pinned interrupts, and minimized context switches. If deterministic timing is essential, offload time-critical parts to a microcontroller or FPGA while the SBC handles higher-level orchestration.
Media, networking, and user-facing tasks
Prioritize reducing software stack depth in the critical path (avoid unnecessary buffering, enable appropriate IRQ priorities, and optimize network stacks). If sub-10 ms latency is required, explore kernel tweaks, network offloads, and, where feasible, dedicated NICs or accelerated software paths.
Data logging and batch processing
Latency here is often less critical than throughput and reliability. Focus on throughput optimizations, efficient file I/O, and asynchronous processing pipelines. Implement buffering and batch writes to minimize per-event latency spikes while preserving data integrity.
Summary
There is no universal number for total timing on SBCs. End-to-end latency depends on the board, the software stack, and the workload. By defining a clear timing budget, identifying bottlenecks across CPU, OS, drivers, I/O, storage, and network paths, and employing targeted measurements and optimization strategies, you can achieve predictable performance tailored to your application. For real-time tasks, aim for tighter budgets and consider real-time or offload options; for user-facing and networked applications, balance latency with throughput and reliability. The key is to measure, iterate, and document the latency profile under realistic conditions.
How much timing should I put sbc 350?
Stock 37 total. For a stock sbc, 8 degree plus 1 degree for 1000 foot of elevation. Full advance, vacuum advance disconnected of 38 degrees. Wherever the idle timing falls, from about 8-20 will be fine.
At what rpm should you set total timing?
(Usually, 3,000 - 3,500 rpm will do it.) Watch the timing mark on the harmonic balancer using the timing light. Rotate the distributor until the timing mark lines up at zero with the light.
How to tell if timing is too advanced?
Some incorrect timing symptoms can include engine knocking or pinging, a loss of power or acceleration, decreased fuel economy, an overheating engine or rough idle.
How to tell if SBC is at TDC?
Into the number one plug. Hole. Watch the tool as it rises or extends outward when it stops moving stop rotating the crank. And check the timing marks look for the mark on the balancer.